In an asynchronous counter, the clock input of each flip-flop except first flip-flop is connected to:

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RRB JE ECE 22 Apr 2025 Shift 2 CBT 2 Official Paper

Answer 1

Explanation:
In an asynchronous counter (also called a ripple counter):

Only the first flip-flop receives the external clock signal.

Each subsequent flip-flop is triggered by the output (Q or Q̅) of the previous flip-flop, not by a common clock.

This causes a ripple effect, where changes propagate sequentially, leading to a slight delay between stages.

Additional Information
Asynchronous Counter

Asynchronous counters are those counters where the clock of the next stage is obtained from the output of the previous state.