The correct answer is: 2) the output of the previous flip-flop

Explanation:
In an asynchronous counter (also called a ripple counter):

Only the first flip-flop receives the external clock signal.

Each subsequent flip-flop is triggered by the output (Q or Q̅) of the previous flip-flop, not by a common clock.

This causes a ripple effect, where changes propagate sequentially, leading to a slight delay between stages.

Additional Information
Asynchronous Counter

Asynchronous counters are those counters where the clock of the next stage is obtained from the output of the previous state.

The correct answer is option 3) 1

Concept:

Let's analyze the given problem statement and options in detail:

Given:

• T = 1
• Current output Q = 0

Let's analyze the state of Q after each clock pulse:

1. Initial state Q = 0
2. After 1st clock pulse: Q will toggle from 0 to 1
3. After 2nd clock pulse: Q will toggle from 1 to 0
4. After 3rd clock pulse: Q will toggle from 0 to 1

Therefore, the output Q after 3 clock pulses will be 1.

Calculation:

We are given that a 100 kHz square waveform is applied to the clock input of the flip-flop.

For a flip-flop, the output frequency is typically half of the input clock frequency, because a flip-flop toggles its state on each clock pulse. This means that for every two input pulses, the output changes state once.

Therefore, if the input frequency is 100 kHz, the output frequency will be:

Output frequency = Input frequency / 2

Substituting the given input frequency:

Output frequency = 100 kHz / 2 = 50 kHz

Hence, the frequency of Q output will be 50 kHz.

Final Answer: The correct answer is option 3: 50 kHz.

• Asynchronous Counter: This type of counter doesn't have a central clock signal for all flip-flops.
• D Flip-Flops: These are used because their output (Q) directly represents the data to be stored when the clock pulse arrives.
• Clock from Previous Flip-Flop: The output (Q) of one flip-flop is connected to the clock input of the next flip-flop in the counter chain.
  This creates a cascading effect where a change in the first flip-flop triggers a change in the subsequent flip-flops one by one.
   

Additional Information

• Independent Clock Signals: This wouldn't create a reliable counting sequence, as the independent clocks might not be perfectly synchronized.
• Alternate Flip-Flops with Same Clock: This configuration wouldn't create a proper counting sequence either.
• Same Clock to All: While technically possible, using a single clock for all flip-flops would defeat the purpose of an asynchronous counter.
  It would be simpler to use a synchronous counter with a common clock for all flip-flops.

The given circuit is a type of SISO.

∴ Latency = n × T_clk .... n = number of flip flops

= 3 × 1 ..... T_clk = \(\frac{1}{f_{clk}}\) = 1 ns

= 3 ns

Now, Throughput = Number of bits/sec

∵ 1 bit = 1 n-sec

∴ Throughput = 10⁹ bits/sec

= 1000 Mbps

Additional Information 

SISO:

• In an n-bit shift register, to enter n bits of data n clock pulses are required
• However, to output data serially (n-1) clock pulses are required

SIPO:

• For n bit serial input data, n clock pulses are required
• To output data, no clock pulse is required

PISO:

• To store n bit data – 1 clock pulse required
• To output data (n-1) clock pulses are required

PIPO:

• 1 clock pulse is required no input data
• No clock pulse is required to output data

Explanation:

Latches and Flip-Flop:

• Latches and flip-flops are the basic elements to store 1-bit of data. Hence they are also known as a one-bit memory element.
• Latches change the output continuously when there is a change in the input, i.e. they are level triggered.
• Flip-flop is a combination of latch and clock. It changes the output that is adjusted by the clock.
• The main difference between a latch and a flip-flop is that a flip-flop has a clock signal, whereas a latch does not.
• We can say that a flip-flop without a clock is a latch.
• Latches are asynchronous, which means that the output of a latch depends on its input.
• Basically, there are 4 types of latches: SR latch, JK latch, D latch, T latch.

T flip flop

The "T Flip Flop" has only one input.

It has only two output states i.e. hold and toggle.

For T = 0, the output is Q_n (Hold state)

For T = 1, the output is \(\overline{Q_n}\) (Toggle state)

The output equation of the T flip-flop is:

Q_n+1 = T ⊗ Q_n

The correct answer is option 2): 4

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2ⁿ (0 to 2ⁿ – 1)
• The largest number that can be stored in the counter = 2ⁿ – 1
• To construct a counter with any MOD number, the minimum number of flip flops required must  satisfy: Modulus ≤ 2ⁿ
• Where n is the number of flip-flops and is the minimum value satisfying the above condition.
• Note: A MOD-N counter is also called as a divide by N counter as the input frequency is divided by the number of states of the counter.

Calculation:

Number no. of flip – flops are required to construct mod-12 counter,

must satisfy: 2ⁿ ≥ 12 The minimum value of n satisfying the above is: n = 4

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops and is the minimum value satisfying the above condition.

Calculation:

The total number of states required when n = 3:

23  ≥  8

The states will vary from (0 to 7)

So the maximum states possible for the counter will be 8.

Concept:

Characteristic table of J-K flip-flop is,

Here, Q(n) is the present state of flip flop and Q(n + 1) is the next state of flip flow.

+ve edge-triggered means the state of flip-flop will only change at the rising edge of the clock.

Therefore, from the characteristic table;

when J = 1, K = 0, Q(n) = 1

Therefore, the correct option will be (2).

An un-clocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

An unclocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

The difference between latches and flip flops is shown

• Latches are level-triggered (outputs can change as soon as the inputs changes)  
• Flip-Flop is edge-triggered (only changes state when a control signal goes from high to low or low to high).
• Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal.
• Level triggering is a type of triggering that allows a circuit to become active when the clock pulse is on a particular level.

Concept:

For an ‘n’ flip flop counter,

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct any mod counter, the minimum number flip flops required such that: Modulus ≤ 2n

Where n is the number of counters.

Calculation:

Number no. of flip – flops are required to construct a mod-10 counter (decade counter) is obtained as:

2n ≥ 10 i.e. n = 4

Note: A MOD-N counter is also called as a divide by N counter as the input frequency is divided by the number of states of the counter.

Truth Table of JK flip flop

When both inputs are low, the next state output will be the present state output.

For J=0 & K=1, the next state output will always be 0 irrespective of the present state.

For J=1 & K=0, the next state output will always be 1 irrespective of the present state.

When both inputs are high, the next state output will be the complement of the present state output.

Characteristics table of JK flip flop

Excitation table of JK flip flop

From the excitation table, it is observed that:

If the present state is 0 and the next state is 1, then J = 1 & k = don't care.