Instruction Pipelining MCQ Quiz in தமிழ் - Objective Question with Answer for Instruction Pipelining - இலவச PDF ஐப் பதிவிறக்கவும்

Here I₃ is dependent both on I₁ and I₂.

I₄ is dependent both on I₂ and I₃.

I₅ is dependent on I₄ only.

NOTE: - We can fetch both the operands in one cycle only, one with the corrected value and other with some dummy value. The operand with dummy value will be updated after Write-Back stage.

Without operand-forwarding:

Without operand forwarding

Total clock cycles = 13

x = 13

With operand-forwarding:

With operand forwarding 

Total clock cycles = 9

y = 9

\(\frac{X}{Y}\)\(=\frac{13}{9}=1.4444\)

= 1.44 (Corrected up to 2 decimal places)

Data:

Number of Instructions = n = 100

Number of stages = 5;

Stage delay = 5 ns

Calculation:

Time taken by five stage pipeline processor of singel instruction = T = Max (150, 120, 150, 160,140)  + stages delay

= 160 + 5 = 165 ns

The time required to execute n instructions with pipeline = [k + (n – 1)]T

= (5 + (100 - 1))×165 = 17160 ns

Concept:

In Horizontal micro-programmed control unit, the control signals are represented in the decoded binary format. Here ‘n’ control signals require n bit encoding.

In Vertical micro-programmed control unit, the control signals are represented in the encoded binary format. Here ‘n’ control signals require ⌈log2n⌉ bit encoding.

Calculation

Number of bits in control word of Horizontal micro-programmed control unit

= 3 + 7 + 10 + 12 + 2 = 34 bits

Number of bits in control word of Vertical micro-programmed control unit

= ⌈log23⌉ + ⌈log27⌉ + ⌈log210⌉ + ⌈log212⌉  + ⌈log22⌉ 

= 2 + 3 + 4 + 4 + 1 = 14 bits

Difference = 34 - 14 = 20 bits.

Concept:

Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is like an assembly line. 

Explanation:

In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.

The main advantages of using pipeline are :

• It increases the overall instruction throughput. 
• Pipeline is divided into stages and stages are connected to form a pipe-like structure.
• We can execute multiple instructions simultaneously.
• It makes the system reliable. 
• It increases the program speed.
• It reduces the overall execution time but does not reduce the individual instruction time.

​Therefore option 2 is the false statement about Pipelining

j = 0

Therefore the number of cycles required to execute 5 instruction is 14.

Steps in the instruction cycle:

• First of all, the opcode is fetched by the microprocessor from a stored memory location.
• Then it is decoded by the microprocessor to find out which operation it needs to perform.
• If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
• After receiving the data, it performs to execute the operation.

Correct sequence: fetch → decode → read effective address → execute

Answer: 1.6

Explanation:  

Number of instructions = 1 Million = 1 * 10 ⁶

Clock Frequency = 2 MHz = 0.5 micro second

So Effective CPI will be = 0.5 * 2 + 0.3*4 + 0.2*5 = 3.2

Execution time = Instruction count * CPI * Cycle time

Execution Time = (1 * 10⁶)*(3.2)*(0.5 * 10^-6) = 1.6 seconds

The correct answer is "option 4".

CONCEPT:

Micro-operations are also known as micro-ops.

They are the atomic or functional operations of a processor.

It is an elementary Central Processing Unit (CPU) operations performed during one clock pulse.

Micro-operations are low-level instructions, used in some designs, to implement complex instructions.

Micro-operations generally perform data stored in one or more registers.

EXPLANATION:

1. Program counter holds the next instruction value to be executed.

Here, MBR <- PC means the value of the program counter will get stored in MBR.

2. MAR <- X means some address value X is storing in MAR so to access memory location X.

3. PC <- Y means storing new instruction value Y to the program counter to access new instruction.

4. Memory <- MBR means MBR register will store its value to Memory. This saves the previous value of PC to memory.

This sequence of instructions matches with Interrupt Service Routine (ISR) since the sequence of instructions saved the address of current instructions into memory.

Then started executing new address by loading new instruction value to Program counter.

Hence, the correct answer is “option 4”.

Additional Information

1. Instruction fetch means fetching the instruction.

2. Operand fetch means fetching the operands.

3. Conditional branch means the program will branch to another instruction after satisfying a condition.

Concept:

Speed up factor is defined as the ratio of time required for non-pipelined execution to that of time received for pipelined execution.

\(S = \frac{{{t_n}}}{{{t_p}}}\)

Where, t_n = time for non-pipelined execution

t_p = time for pipelined execution

S = speed up factor

Calculation:

Given, t_n = 50 ns

t_p = 10 ns

\(S = \frac{{50}}{{10}} = 5\)

Extra Information:

Speed up factor is also defined as:

\(S = \frac{{nk}}{{n + \left( {k - 1} \right)}}\)

n = number of instructions

k = number of stages in the pipeline.

Formula:

\(Speed\;up = \frac{{execution\;time\;without\;pipeline}}{{execution\;time\;with\;pipeline}}\)

Explanation:

Given:

Delay of stage S₁ = 10 ns

Stage delays are represented as :

Execution time with pipeline (T_p) = max {all stage delays}

= 10 ns

Execution time without pipeline(T_n) = sum of all stage delays

= 10 + 5 + 10 + 5 + 10 = 40 ns

\(Speed\;up = \;\frac{{40}}{{10}} = 4\)