Instruction Pipelining MCQ Quiz - Objective Question with Answer for Instruction Pipelining - Download Free PDF

The correct answer is Instruction Fetch.

Key Points

• Instruction fetch is the process of reading an instruction from memory into the processor.
• The sequence of micro-operations given corresponds to the steps involved in fetching an instruction from memory:
  • MBR ← PC: The content of the Program Counter (PC) is transferred to the Memory Buffer Register (MBR).
  • MAR ← X: The content of the register X is transferred to the Memory Address Register (MAR).
  • PC ← Y: The content of the register Y is transferred to the Program Counter (PC).
  • MEMORY ← MBR: The content of the MBR is transferred to the memory.
• This sequence is typical of the steps taken to fetch an instruction from memory, making instruction fetch the correct answer.

Additional Information

• The Program Counter (PC) holds the address of the next instruction to be fetched.
• The Memory Address Register (MAR) holds the address of the memory location to be accessed.
• The Memory Buffer Register (MBR) holds the data to be written to memory or the data read from memory.
• Fetching an instruction involves reading the instruction from memory into the instruction register.
• This process is crucial for the CPU to understand which operation to execute next.

The correct answer is Option 2: B, D, A, C.

Key Points

• The instruction cycle is the process by which a computer retrieves, decodes, and executes an instruction.
• The correct sequence of operations is:
  • Fetch the information (B): The instruction is fetched from memory.
  • Decode the instruction (D): The fetched instruction is decoded to understand the operation to be performed.
  • Read the effective address (A): The effective address of the data required for the operation is determined.
  • Execute the instruction (C): The instruction is executed and the desired operation is performed.

Additional Information

• The instruction cycle is fundamental to the operation of all computers and involves multiple steps to ensure that the correct operations are performed accurately.
• Each step in the cycle is crucial for the correct execution of instructions, ensuring that the computer processes data efficiently.
• Understanding the instruction cycle is important for those studying computer architecture and assembly language programming.

The correct answer is Option 2: D, C, A, B

Explanation:

The correct sequence of stages for fixed-point multiplication of 8-bit integers is as follows:

1. Stage D: Generates eight partial products. This stage is the initial step where the multiplicand and multiplier are combined to produce partial products.
2. Stage C: Consists of two levels of four CSAS (Carry Save Adders). This stage processes the partial products to reduce the number of operands.
3. Stage A: Consists of two CSAS and it merges four numbers from the previous stage. This further reduces the operands.
4. Stage B: Is a CPA (Carry Propagate Adder), which adds up the two numbers. This final stage produces the final product by adding the last two numbers.

The correct answer is Reservation Table.

• A reservation table is used in dynamic pipelines to keep track of the usage of functional units over time.
• When a nonlinear pattern is followed, the reservation table becomes more interesting because it needs to efficiently handle the dynamic allocation and deallocation of resources.
• This dynamic nature allows the pipeline to adapt to varying workloads and optimize the performance.
• The reservation table helps in avoiding conflicts and ensuring that the functional units are utilized effectively, especially when there are dependencies among instructions.
• It is crucial in maintaining the pipeline's efficiency and preventing stalls that can occur due to resource contention.

• Reservation tables are used in various stages of instruction execution to track the availability and scheduling of resources.
• They play a vital role in superscalar and out-of-order execution architectures by managing multiple instructions simultaneously.
• In a complex pipeline, the reservation table helps in reducing latency and improving throughput by efficiently scheduling instructions.
• Understanding the reservation table is essential for optimizing the performance of modern processors and designing efficient instruction pipelines.

The correct answer is 2·24 

Explanation:

The formula for finding the total CPI is given below

CPI = ∑ Frequency_i * CPI_i

Frequencyi = IC_i / Instruction count

CPI = (0.60 * 1) + (0.18 * 2) + (0.12 * 4) + (0.10 * 8)

CPI = 2.24

• The Steps required by the CPU to fetch and execute an Instruction is called an instruction cycle. It consists of fetch and executes cycle.
• Instruction cycle (IC) = Fetch cycle (FC) + Execution cycle (EC)
• The time required by the microprocessor to complete the operation of accessing memory or I/O devices is called a machine cycle.
• Clock time is a known time state. It is reciprocal of clock frequency.
• Instruction cycle > Machine cycle > Clock cycle (time state)

Steps in the instruction cycle:

• First of all, the opcode is fetched by the microprocessor from a stored memory location.
• Then it is decoded by the microprocessor to find out which operation it needs to perform.
• If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
• After receiving the data, it performs to execute the operation.

 

Correct sequence: fetch → decode → read effective address → execute

The correct answer is option 2

Concept:

The segments are separated by registers R_i that holds the intermediate results between the stages.

Data:

Stage delay and corresponding register delay given

S1 = 5 ,

S2 = 6 ,

S3 = 11,

S4 = 8,

And corresponding register delay is 1 for each stage

Number of stage = 4

Explanation:

Time is taken to execute N instructions in non-pipelined implementation will be =(5+6+11+8)N = 30×N

Clock period for pipelined implementation =max(5,6,11,8) + 1 = 12 ns

Time is taken to execute N instructions in pipelined implementation will be = (4 + N-1)12 ≈ 12×N (N is very large)

Speedup = \({30N\over12N }=2.5\)

Concept -

XY + XYZ + YZ = (X × Y) + (X × Y × Z) + (Y × Z) = (X × Y) + (X × Y + Y) × Z

The instructions are non-pipelined and cycles for each instruction is mentioned. Therefore,

X × Y - takes 2 cycles

X × Y + Y - takes 1 cycles (X × Y already done)

(X × Y + Y) × Z - takes 2 cycles

(X × Y) + (X × Y + Y) × Z - takes 1 cycle

Hence, total cycles = 2 + 1 + 2 + 1 = 6

Data:

For a non-pipelined processor,

Clock cycles to complete one instruction = 5

Instruction operating frequency = 2.5 GHz

One clock cycle time = 1/ (2.5 GHz) = 0.4 ns

For N number of instructions, clock cycles required = 5N

Time taken to complete 5n clock cycles = 0.4*5n = 2N ns

For a pipelined processor,

Stages of pipeline = 5

Overheads associated = 2 GHz

One clock cycle time = 1/ (2 GHz) = 0.5 ns

For n instructions, clock cycles required

 

Instruction type	Number of such instructions	% causing stalls	Number of clock cycles
Memory	0.3N	5% of 0.3N	50
ALU	0.6N	None	0
Branch	0.1N	50% of 0.1N	2

 

Therefore, time taken by pipelined processor:

0.6N (1) + 0.3N [0.05 (1 + 50) + 0.95 (1)] + 0.1N [0.5 (1 + 2) + 0.5 (1)] cycles

= 1.85N cycles

= 1.85N/2 ns

= 0.925N ns

Speedup = \(\frac{{2{\rm{N}}}}{{0.925{\rm{\;N}}}}\) = 2.162

Data:

No. of pipeline segments = stages in pipeline, n = 5

Clock cycle time per operation = clock cycle per stage = 20 ns

No. of instructions = 100

Formula:

\({\rm{Spee}}{{\rm{d}}_{{\rm{up}}}} = {\rm{}}\frac{{{{\rm{T}}_{{\rm{without\;pipeline}}}}}}{{{{\rm{T}}_{{\rm{with\;pipeline}}}}}}\)

Calculation:

T_{without pipeline} = no. of instructions × stages in pipeline × clock cycle per stage

= 100 × 5 × 20

T_{with pipeline} = (time for pipelined execution without stalls) + (overhead due to stalls)

= (5 + 99) × 20 + 20 × 20 = 124 × 20

\(Spee{d_{up}} = \frac{{500 \times 20}}{{124 \times 20}} = 4.03\)

Explanation:

→ For calculating the time for pipelined execution without stalls, it is considered that 1^st instruction takes up an entire clock cycle, while each instruction after that takes up only the maximum time from all the segments. In our case, all the segments took an equal time of 20ns (1 Clock) hence,

time for pipelined execution without stalls = time required for first instruction + (n - 1) instructions taking 20 ns each = 5 × 20 + (100 - 1) × 20, that is we needed 104 clocks for complete execution

→ Overhead is calculated because it is mentioned in the question that every five cycles, a bubble due to data hazard has to be introduced in the pipeline. Hence ⌊ 104/5 ⌋ = 20 such overheads, each requiring 20ns of service time = 20 × 20

Machine Cycle: Time taken to execute one OPERATION is known as a machine cycle.  One instruction will contain 1 to 5 machine cycles.

T-State: The portion of a machine cycle executed in one internal clock pulse is known as T-state.

Steps in the instruction cycle:

• First of all, the opcode is fetched by the microprocessor from a stored memory location.
• Then it is decoded by the microprocessor to find out which operation it needs to perform.
• If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
• After receiving the data, it performs to execute the operation.

 

Correct sequence: fetch → decode → read effective address → execute

Concept:

Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is like an assembly line. 

Explanation:

In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.

The main advantages of using pipeline are :

• It increases the overall instruction throughput. 
• Pipeline is divided into stages and stages are connected to form a pipe-like structure.
• We can execute multiple instructions simultaneously.
• It makes the system reliable. 
• It increases the program speed.
• It reduces the overall execution time but does not reduce the individual instruction time.

Total Instruction = 100

Instruction Fetch, Instruction Decode, Operand Fetch, and Writeback (WB) performed in 1 cycle.

PO stage:

40 instructions take 3 cycle

35 instructions take 2 cycles

25 instructions take 1 cycle

Average number of cycles  = (40*3+35*2+25*1)/100 = 2.15 cycles.

On an average first instruction completed in 1+1+1+1+2.15 cycles

Remaining 99 instruction will takes 99*2.15 = 212.85 cycle

Total number of cycles is 6.15+212.85 = 219 cycles.

Concept:

Speed up factor is defined as the ratio of time required for non-pipelined execution to that of time received for pipelined execution.

Data:

Time for non-pipelined execution per task = t_n = 50 ns

Time for pipelined execution per task =  tp = 10 ns

Number of stages in the pipeline = k = 6

Number of tasks = 500

Formula

\(S = \frac{{{T_n}}}{{{T_p}}}\)

S = speed up factor

Calculation:

Time for non-pipelined = Tn = t_n × Number of tasks

Time for non-pipelined = T_n =  50 × 500

Time for pipelined = Tp​ = 1st task × k × t_p + (All Remaining Tasks (k - 1)) × t_p

Time for pipelined = Tp​ =  1 × 6 × 10 + (500 - 1) × 10

\(S = \frac{{T_n}}{{T_p}} = 4.95\)

Data:

Number of Instructions = n = 100

Number of stages = 5;

Stage delay = 5 ns

Calculation:

Time taken by five stage pipeline processor of singel instruction = T = Max (150, 120, 150, 160,140)  + stages delay

= 160 + 5 = 165 ns

The time required to execute n instructions with pipeline = [k + (n – 1)]T

= (5 + (100 - 1))×165 = 17160 ns