Interrupts of 8085 MCQ Quiz - Objective Question with Answer for Interrupts of 8085 - Download Free PDF

The correct answer is: 2) RST 7.5

Explanation:

In the 8085 microprocessor, the RST 7.5 interrupt has unique characteristics:

• Edge-Triggered:
• RST 7.5 is positive-edge sensitive, meaning it triggers when the signal transitions from LOW to HIGH.
• It can be activated by a short pulse (minimum 500 ns wide).
   

Other RST Interrupts:

RST 6.5 and RST 5.5: Level-sensitive (require the signal to remain HIGH until acknowledged).

RST 4.5: Not a standard interrupt in 8085.6

Explanation:

Microprocessor 8085 Address/Data Buffer

Definition: In the context of microprocessors, a buffer is a temporary storage area used to hold data temporarily while it is being moved from one place to another. The Address/Data buffer in the 8085 microprocessor plays a crucial role in interfacing the microprocessor with memory and other peripherals. It is used to manage the flow of data and addresses between the microprocessor and external devices.

• 8 bit: The 8085 microprocessor has an 8-bit data bus, which means it can handle 8 bits of data simultaneously. The data bus is used to transfer data between the microprocessor and memory or peripherals. An 8-bit bus allows for a data range of 0 to 255 (in decimal).
• Bi-directional: The term bi-directional indicates that the data bus can be used to send data to and receive data from memory and peripherals. This is essential for the operation of a microprocessor, as it needs to both read data from and write data to external devices. In the case of the 8085 microprocessor, the Address/Data buffer must be able to handle data moving in both directions to facilitate proper communication and data transfer.

The Address/Data buffer in the 8085 microprocessor serves two purposes:

1. Address Bus: During the first part of the memory access cycle, the buffer is used to send the address from the microprocessor to the memory or peripheral. This address specifies the location in memory or the specific peripheral to be accessed.
2. Data Bus: Once the address has been specified, the buffer is then used to transfer data. Depending on the operation, this data might be sent from the microprocessor to the memory/peripheral (write operation) or from the memory/peripheral to the microprocessor (read operation).

In summary, the Address/Data buffer in the 8085 microprocessor is 8-bit and bi-directional, as it needs to handle both the addressing and data transfer functions in a seamless manner.

The correct answer is 34H
Concept:

Branching address of RST 6.5 is 34H

Key Points

Additional Information

• 8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR
• Out of these, INTR is non vectored interrupt and remaining interrupts are vectored interrupts.

​

TRAP is a Nonmaskable, highest priority, and hardware interrupts.

1) When microprocessors receive interrupt signals through pins (hardware) of the microprocessor, they are known as Hardware Interrupts.

2) Five hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5 and INTR

3) The priority of interrupts in the decreasing order:

TRAP > RST 7.5 > RST 6.5 > RST 5.5​

4) Out of these, INTR is a non-vectored interrupt and the remaining interrupts are vectored interrupts.

Edge Triggered Interrupts:

1. TRAP

2. RST 7.5

Level-Triggered Interrupts:

1. TRAP

2. RST 5.5

3. RST 6.5

4. INTR

TRAP is both level and positive edge sensitive it means that TRAP makes a low to high transition and remains high until it is acknowledged.

Since the TRAP input has the highest priority, it is used for catastrophic events such as power failure, parity errors, and other events that require immediate attention.

For 8085 the interrupt service routine address is given as:

RST 4.5 (TRAP)

ISR address: 4.5 × 8 = (36)10 = (0024) H

RST 5.5

ISR address: 5.5 × 8 = (44)10 = (002C) H

RST 6.5

ISR address: 6.5 × 8 = (52)10 = (0034) H

RST 7.5

8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR

Out of these, TRAP is non-maskable and the remaining all are maskable interrupts.

Key Notes:

Vectored Interrupt :

In this type of interrupts the interrupting device directs the processor for Interrupt service routine.

Maskable

An interrupt whose interrupt service can be stopped from being serviced temporarily is called Maskable Interrupt.

Non Maskable 

An interrupt whose service cannot be delayed is called Non-Maskable Interrupt

The correct answer is: 2) RST 7.5

Explanation:

In the 8085 microprocessor, the RST 7.5 interrupt has unique characteristics:

• Edge-Triggered:
• RST 7.5 is positive-edge sensitive, meaning it triggers when the signal transitions from LOW to HIGH.
• It can be activated by a short pulse (minimum 500 ns wide).
   

Other RST Interrupts:

RST 6.5 and RST 5.5: Level-sensitive (require the signal to remain HIGH until acknowledged).

RST 4.5: Not a standard interrupt in 8085.6

Edge Triggered Interrupts:

1. TRAP

2. RST 7.5

Level-Triggered Interrupts:

1. TRAP

2. RST 5.5

3. RST 6.5

4. INTR

TRAP is both level and positive edge sensitive it means that TRAP makes a low to high transition and remain high until it is acknowledged.

Since the TRAP input has the highest priority, it is used for catastrophic events such as power failure, parity errors, and other events that require immediate attention.

​

TRAP is a Nonmaskable, highest priority, and hardware interrupts.

1) When microprocessors receive interrupt signals through pins (hardware) of the microprocessor, they are known as Hardware Interrupts.

2) Five hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5 and INTR

3) The priority of interrupts in the decreasing order:

TRAP > RST 7.5 > RST 6.5 > RST 5.5​

4) Out of these, INTR is a non-vectored interrupt and the remaining interrupts are vectored interrupts.

For 8085 the interrupt service routine address is given as:

RST 4.5 (TRAP)

ISR address: 4.5 × 8 = (36)10 = (0024) H

RST 5.5

ISR address: 5.5 × 8 = (44)10 = (002C) H

RST 6.5

ISR address: 6.5 × 8 = (52)10 = (0034) H

RST 7.5

8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR

Out of these, TRAP is non-maskable and the remaining all are maskable interrupts.

Key Notes:

TRAP is a vectored interrupt also known as RST 4.5 

The address of various vectored interrupts are given as:

For 8085 the interrupt service routine address is given as:

RST 4.5 (TRAP)

ISR address: 4.5 x 8 = (36)₁₀ = (0024) H

RST 5.5

ISR address: 5.5 x 8 = (44)₁₀ = (002C) H

RST 6.5

ISR address: 6.5 x 8 = (52)₁₀ = (0034) H

RST 7.5

ISR address: 7.5 x 8 = (60)₁₀ = (003C) H

When TRAP interrupt is triggered in an Intel 8085A, the program control is transferred to 0024 H

Concept:

There are two kinds of interrupts in 8085:

Hardware Interrupts:

The hardware interrupts are initiated by an external device by placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor executes an interrupt service routine (ISR).

1. INTR

2. TRAP

3. RST 7.5

4. RST 6.5

5. RST 5.5

Software Interrupts:

These instructions are inserted at desired locations in a program. While running a program, if a software interrupt instruction is encountered, then the processor executes an interrupt service routine (ISR)

1. RST 0

2. RST 1

3. RST 2

4. RST 3

5. RST 4

6. RST 5

7. RST 6

8. RST 7

Hence there are total 13 interrupts in 8085.

Calculation:

The address line can be calculated as:

​In 8085 microprocessor, after the execution of RST 5 instruction, the program control shifts to its vector address.

The vector address for these interrupts can be calculated as follows:

Interrupts no. ×  8 = vector address

For RST 5:

5 ×  8 = 40 = 28 H

∴ The vector address for interrupts RS T 5 is 0028H.

Hence option (2) is the correct answer.

Important Points

The vector addresses for software interrupts are given by the table below: