What are the logic levels in case of TTL logic using +5V as V_CC?

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ALP CBT 2 Electronic Mechanic Previous Paper: Held on 21 Jan 2019 Shift 2

Answer 1

TTL (Transistor-Transistor Logic):

A TTL input signal is defined as "low" when between 0 V and 0.8 V with respect to the ground terminal.
A TTL input signal is defined as "high" when between 2 V and 5 V.
if a voltage signal ranging between 0.8 V and 2.0 V is sent into the input of a TTL gate, there is no certain response from the gate and therefore it is considered "uncertain" (precise logic levels vary slightly between sub-types and by temperature).

F1 Tapesh Madhu 06.08.20 D2

TTL outputs are typically restricted to narrower limits of between 0.0 V and 0.4 V for a "low".
TTL outputs are typically restricted to narrower limits of between 2.4 V and 5 V for a "high", providing at least 0.4 V of noise immunity.

26 June 1

CMOS:

For a CMOS gate operating at a power supply voltage of 5 volts,
The acceptable input signal voltages range from 0 volts to 1.5 volts for a “low” logic state and 3.5 volts to 5 volts for a “high” logic state.
Acceptable output signal voltages range from 0 volts to 0.05 volts for a “low” logic state, and 4.95 volts to 5 volts for a “high” logic state:

F1 Tapesh Madhu 06.08.20 D1